1. Field of the Invention
This invention relates in general to a method of fabricating semiconductor integrated circuit (IC) devices and, in particular, to a method of fabricating dynamic random-access memory (DRAM) devices. More particularly, this invention relates to a method of fabricating contact openings for DRAM devices.
2. Description of Related Art
Semiconductor DRAM devices are widely used in various digital electronic equipment, and is virtually indispensable in many state-of-the-art digital computing electronics in information industry. FIG. 1 of the accompanying drawings is a schematic diagram showing a memory cell unit of a typical DRAM device. As is illustrated, a transfer transistor T and a storage capacitor C constitute a basic memory cell unit for a DRAM. The source terminal of the transfer transistor T is connected to a corresponding bit line BL for the memory cell unit in the array, while the drain thereof is connected to one electrode 6 of the storage capacitor C. The gate electrode of the transfer transistor T is strobed by a word line WL of the memory array. Electrode 8 of the storage capacitor C opposite to electrode 6 is connected to a fixed electric potential of the DRAM system. Sandwiched between the electrodes 6 and 8 of the storage capacitor C is a layer of dielectric material 7.
As is well known in the art, the storage capacitor C is used to store the data bit in the memory cell unit by of its charged or discharged status, and the capacitor should be able to hold a sufficient amount of electric charge. Inherent structural characteristics of DRAM memory cell units inevitably lead to leakage of charge stored in the storage capacitor. Without a sufficiently large capacitance, the memory cell unit can not sustain an electrical charge above a threshold level during normal cell unit refresh cycles, and data loss results.
FIGS. 2A-2B of the drawings are cross-sectional views of a DRAM memory cell unit as it would appear at various; stages of a conventional process of making contact openings for the cell unit. In the capacitor-over-bit line structural configuration for DRAM devices, the contact opening is used to install a via that is used to electrically connect the bottom electrode (6 in FIG. 1) of the storage capacitor (C) to the source/drain region of the transfer transistor (T). With reference to FIG. 2A, a memory cell transistor, together with an oxide layer 14 for its electrical insulation, bit lines 16, and a second oxide layer 18 for insulating the bit line 16, is formed on the substrate 10 of the semiconductor device being fabricated. The transistor includes a gate electrode 12, sidewall spacer 13 for the gate electrode 12, and a pair of source/drain regions 15. The first oxide layer 14 and the second oxide layer 18 can be formed of silicon oxide, and the bit line 16 may be formed of doped polysilicon. The second oxide layer 18 not only covers the surface of the bit lines 16, but further, fills into the spacing between consecutive bit lines 16. The spacing between bit lines 16 is substantially located above the corresponding source/drain region 15 of the cell unit transistor. In other words, the bit lines 16 themselves are virtually misaligned vertically with the transistor source/drain region 15.
Referring to FIG. 2A, a polysilicon or silicon nitride layer 20 is formed covering the surface of the second oxide layer 18 in, for example, a low-pressure chemical vapor deposition (LPCVD) procedure. If polysilicon is used for deposition, it can be further doped with impurities.
Then, as illustrated in FIG. 2B, a photolithographic procedure is employed to form a contact opening in the structure. This location is virtually above the transistor source/drain region 15 as shown in the drawing. This includes forming a photoresist layer that exposes the location of the contact opening, and subsequently etching anisotropically into the doped polysilicon or silicon nitride layer 20, the second oxide layer 18, and the first oxide layer 14. The anisotropic etching concludes when the transistor source/drain region 15 is exposed and the contact opening 22 is now formed.
In this conventional fabrication procedure, however, bit lines 16 may be exposed laterally in the sidewall of the contact opening 22 if the alignment of the photolithographic procedure was not controlled properly. If this was the case, the electrically conductive via formed in the contact openings 22 may be short-circuited with the bit lines 16. The yield deteriorates as a result of such short-circuiting.
Further, in the fabrication procedure for making the capacitor-over-bit line structural configuration for DRAM devices, the spaces left between the contact opening and the transistor gate electrode and between the contact opening and the polysilicon layer used as the word line become uncomfortably narrow. This requires a reduction of the size of the contact opening. In other words, the contact openings are required to have a smaller diameter. However, under a 0.35 .mu.m design rule, the photolithographic procedure itself, or the etching cross-sectional profile control employed to effect the reduction of contact opening sizes become difficult to implement. This is because deep ultraviolet light must be used. Deep ultraviolet photolithography has poor control capability over etching profiles. Further, deep ultraviolet light is virtually no more suitable for fabrication procedures employing a resolution finer than 0.35 .mu.m.